Assuming that the stored value of the proposed RHBD 10Tmemory cell is 1 in digital logic, i.e., Q = 1, QN = 0, S1 = 1,and S0 = 0, as shown in Fig.
1. It is easily concluded that theproposed RHBD 10T memory cell is steadily maintaining the storedvalue when WL is driven by a low voltage (WL = 0). Before normalread operation, due to precharge circuitry, the voltages of the bit linesBL and BLN will be raised to 1 in digital logic.
In read operation,WL is in high mode (WL = 1), and then two access transistorsN3 and N4 are turned ON immediately. Nodes Q, QN, S1, andS0 are keeping the stored value, and the voltage of bitline BL isalso unchanged. However, the voltage of bitline BLN is decreaseddue to the discharge operation through ON transistors N1 and N3.Once the voltage difference of bitlines is a constant value which hasbeen confirmed in the differential sense amplifier connecting withtwo bitlines, the stored digital signal in memory cell will be outputas soon as possible. The purpose of write operation is to change thestored logical value correctly.
Therefore, before write operation, dueto the write circuitry, the voltages of bitline BL will be 0 in digitallogic. Contrary to the voltage of bitline BL, the voltage of bitlineBLN will be 1. When the voltage of WL is supply voltage VDD(WL = 1), write operation is executed. Transistors N2, P2, P3, andP6 are turned ON. At the moment, the states of transistors N1, P1,P4, and P5 will be OFF, so that the logical value of this memorycell is rightly changed to 0. Therefore, write operation can also becompleted successfully.
