Assuming value when WL is driven by

Assuming that the stored value of the proposed RHBD 10T
memory cell is 1 in digital logic, i.e., Q = 1, QN = 0, S1 = 1,
and S0 = 0, as shown in Fig. 1. It is easily concluded that the
proposed RHBD 10T memory cell is steadily maintaining the stored
value when WL is driven by a low voltage (WL = 0). Before normal
read operation, due to precharge circuitry, the voltages of the bit lines
BL and BLN will be raised to 1 in digital logic. In read operation,
WL is in high mode (WL = 1), and then two access transistors
N3 and N4 are turned ON immediately. Nodes Q, QN, S1, and
S0 are keeping the stored value, and the voltage of bitline BL is
also unchanged. However, the voltage of bitline BLN is decreased
due to the discharge operation through ON transistors N1 and N3.
Once the voltage difference of bitlines is a constant value which has
been confirmed in the differential sense amplifier connecting with
two bitlines, the stored digital signal in memory cell will be output
as soon as possible. The purpose of write operation is to change the
stored logical value correctly. Therefore, before write operation, due
to the write circuitry, the voltages of bitline BL will be 0 in digital
logic. Contrary to the voltage of bitline BL, the voltage of bitline
BLN will be 1. When the voltage of WL is supply voltage VDD
(WL = 1), write operation is executed. Transistors N2, P2, P3, and
P6 are turned ON. At the moment, the states of transistors N1, P1,
P4, and P5 will be OFF, so that the logical value of this memory
cell is rightly changed to 0. Therefore, write operation can also be
completed successfully.


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