Von bus and instruction bus can transfer

Von Neumann started designing computer architecture from 1946. Prototype IAS (Institute for Advanced study) machine developed using Von Neumann architecture. Von Neumann architecture has Main Memory, CPU and Input or Output interface. Program and Data is stored in main memory. CPU has ALU and program control unit. Program control unit fetches instructions from main memory and interprets them. ALU (Arithmetic Logic unit) executes the instructions and results can stored back to main memory. Von Neumann architecture has only single bus for both program and data.

Unable to transfer program fetch instructions and data in parallel. Harvard architecture has two memories. One for data and other for Program instructions. Two busses, data bus and instruction bus can transfer data in parallel.

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Strict separation between code and instruction memories, data cannot be used as code and vice versa. Von Neumann can use code as data and vice versa. Modified hardware architecture introduced two cache memories. Those are data and instruction cache memories and unified main memory to resolve hardware architecture issues.

Data and Instruction cache memories are connected in between main memory and CPU via data and instruction busses. Data and instructions are loaded to cache before the execution starts. Cache means a temporary memory, it holds the present and future instruction and data to be executed. Cache memory operates at higher frequency than main memory and program executions will be faster. Complex instruction set computing (CISC) has very complex variable length instructions. CISC instruction can load, add and store with single instruction. RISC (Reduced instruction set computing) architectures has Fixed length simple instructions.

RISC instruction can be executed in single cycle. CISC can take more than single cycle as it is complex microprogram conversion, execute and store can be performed. CISC decoding takes time and it prevent pipelining in the past. Modern CISC processors instructions split into micro operations like RISC. CISC emphasis on processor hardware and more transistors are used. RISC Processor Compilers are more complex and parallel pipelining will be done to execute instructions with in single cycle. CISC example are intel x86, x64 and AMD. RISC Processor examples are ARM, MIPS and TI.

ARM Ltd licenses IP to chip manufactures. RISC ARM processors are power efficient and used widely in mobiles, automotive, tablets, embedded systems and real time systems. Most of the modern processors are offering SIMD (Single instruction multiple data). That means, if the processor is 32-bit, it can perform four additions (8bit) in single cycle. Texas instruments designed VLIW (Very long Instruction word) architecture. TI processor contains 8 execution units.

That means eight 32-bit operations can be performed in single cycle. Multi core processors shares common bus and Level 2 cache memory. More operations can be performed using multi threads and multi process run in parallel and synchronize them. Co-processors and Hardware accelerators are developed further to support main processors.

Hardware accelerators can achieve high performance at very low frequency. This helps portable devices chare last longer. GPU (Graphical processing Unit) renders 2D and 3D graphics very fast at lower frequency. The modern computer architecture increasing processor complexity, smaller size, more special registers, more addressing modes, dedicated engines for vector processing, compiler level optimizations and better pipelining. Two approaches identified to compare RISC and CISC. Quantitative approach: write a program and compile and execute on both RISC and CISC to check code size and speed. Qualitative approach: Support of high level languages like Java and how best hardware is utilized. Tried Qualitative and quantitative approaches to compare CISC and RISC.

Many problems observed to do such comparison. Software program performance depends on type of computations involved. One program may run fast on CISC and other may run fast on RISC. It is totally program dependent and how good the compilers can optimize the code. There is no technology available to verify how best compilers are optimizing and this can lead to hardware performance issue. Modern RISC processors like Power PC has characteristics of RISC and CISC. CISC processors are splitting instructions as Micro Ops like RISC. CISC is used in desktops, servers and high-performance systems.

RISC are power efficient and used in Toys, mobile and automotive etc. RISC processor became more complex and operating at higher frequency to achieve higher speed. RISC widens market to laptops, netbooks and tables.

Both CISC and RISC have pros and cons. Comparison is irrelevant. Intel and ARM introduced 64-bit processors. Both support SIMD, virtualization and Vector extensions.

ARM provides Thumb (16-bit instruction set), Thumb2, Java execution. ISA’s RISC and CISC are equally positioned in market and continue to innovate new few features in hardware and compilers.


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